Practical Validation

This document explains how to reproduce the experiments discussed in Section V of the paper, which aim at validating the practical feasibility of the proposed approach.

The case-study has been designed by using the Vivado Design Suite for the Zybo board equipped with the Zynq-7010 System-on-Chip.

Note: To replicate this experiment it necessary to dispose of the Zynq-7010 platform. In particular, the experiments have been performed on the Zybo board produced by Digilent.

The experiments are based on a case-study application composed of four standard algorithms implemented both as HW-Tasks (executed on the FPGA) and SW-Tasks (executed on the CPU):

The HW-tasks have been designed with the Vivado high-level synthesis tool, while their corresponding software versions have been implemented in the C language. The package provided with this artifact evaluation includes both a compiled version and the source code of the case-study. The former one is provided to ease the reproduction of the experiments without undertaking the compilation of the source code.

The remainder of this document is organized as follows:

  1. Package - describes the content of the folders included in the provided package;
  2. Replicating the experiments - reports the instructions to replicate the experimentis by using the compiled version of the case-study;
  3. How to build the case-study from the source code - describes how to re-build the case-study starting from its source code.


The package provided with this artifact evaluation is available as a zip file.

The package is composed of the following directories:

Replicating the experiments

This section describes how to replicate the experiments presented in Section V of the paper. To ease the reproduction of the experiments, we provided a ready-to-use set of partial bitstreams available in the sd-image directory of the provided package. The content of such a directory must be copied into a SD card (formatted as FAT) which has to be connected to the Zybo board.


To run the experiments it is required to install the Vivado Suite. A logic analyzer is also required to collect the output data of the response-time experiment described in section Section V.C.2 of the paper.

The experiments can be executed by using the SDK (Software Development Kit) included in the Vivado suite. We recommend to launch the SDK from Vivado when the project (available in the vivado folder of the package) is open: in this way the workspace will be automatically configured for the current project (named Test). The workspace of the project includes: source files, board support package and hardware platform wrapper.

Vivado SDK is a customized version of the Eclipse IDE, therefore the software project can be build following the standard building process of Eclipse (please refer to the official Eclipse Help).

Response-time experiment (Section V.C.2)

The purpose of this experiment is to evaluate the longest observed response times in a scenario where the number of HW-tasks exceeds the number of slots.

To replicate the Response time experiment the software project must be build (inside the SDK environment) with the release configuration (preconfigured in Eclipse). Once the building process has finished, the Programmable Logic must be configured with the full bitstream, which is a large bitstream that also includes the static configuration of the FPGA (full.bit included in the bitstreams folder). This operation can be performed by using the Program FPGA button in the SDK toolbar. When the configuration is finished, the experiment can be launched though the Run menu (Run As -> Launch on Hardware (GDB)).

Each of the four tasks described in Section V-C is assigned to one of the pins of the JF Pmod connector available on the Zybo board (please refer to the datasheet of the board to identify such a connector). The tasks have been programmed to (i) rise their correspondent pin at activation and (ii) drop back to zero the pin when the computation completes. Analogously, an additional pin (number 5) is provided to monitor the reconfiguration times. The following table summarizes the pin mapping:

JF Pin Purpose
1 Sobel Task
2 Blur Task
3 Sharp Task
4 Mult Task
5 Reconfiguration

The results of this experiment can be collected using a logic analyzer connected to the JF Pmod connector.

Speedup evaluation experiment (Section V.C.1)

This experiment has been conceived to measure the speedup factors achievable with an implementation in programmable logic (i.e., to be executed on the FPGA) with respect to pure software implementations.

The measurements of the execution times are performed as follows. Four sub-experiments have been defined, each conceived to meaure the execution times of both the HW- and the SW-task implementation of each algorithm in the case-study. For each algorithm, first the HW implementation is executed and then its SW counterparts. Each sub-experiment will run for a fixed number of minutes that can be specified in the running_time_minutes constant variable (available in the source code).

To replicate one of such sub-experiments, say the one related to the sharp filter, the following modifications to the source code included in the project are needed:

With these modifications the project can be rebuild and then launched with the same procedure described for the previous experiment. When the run completes, a textual log is transmitted via the serial port. To this end, please connect to the serial port of the Zybo board and enable a software to listen it (e.g., like HTerm).

How to build the case-study from the source code


In order to build the case-study from the sources, it is required to install the Vivado Suite. Moreover, to build the HW-tasks, the Vivado suite must comprise the licenses for High-Level Synthesis (HLS) and Partial Reconfiguration (PR).
The case study has been developed and tested using Vivado 2015.4 on GNU/Linux x86_64. If a different version of Vivado, or a different operating system is used, some minor adjustment to the design and to the building process may be required.

Bulding the HW-Tasks

  1. Open the system design with Vivado and launch the synthesis run;
  2. For each HW-Task launch the high-level synthesis process using the run.tcl script;
  3. Copy the following elements into the partial reconfiguration folder:
  4. Launch the partial reconfiguration flow using the design.tcl script;
  5. Once the bitstreams have been generated they can be renamed and copied inside the /bits directory of the SD card.

Building the SW-Tasks and the RTOS

The software part of the design can be build by using the SDK included in the Vivado suite. The source-code of the software is located inside the .sdk sub-folder of the system project. Vivado SDK is a customized version of the Eclipse IDE, therefore the project can be build following the usual building process.