RTSS 2016 - Artifact Evaluation

This tutorial explains how to reproduce the experiments discussed in the paper

A. Biondi, A. Balsini, M. Pagani, E. Rossi, M. Marinoni, G. Buttazzo - “A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs”, IEEE Real-Time Systems Symposium (RTSS 2016), to appear, November 2016

In the paper, we report on two different experimental studies. For each of them we prepared a separate page.

Schedulability experiments (Section VI)

These experiments aimed at evaluating the performance of the proposed approach in terms of schedulability analysis with synthetic workload. The experiments are performed to verify the schedulability under different configurations and are obtained by applying the sufficient response-time analysis presented in Section IV.

Please follow THIS LINK to enter the page dedicated to such experiments.

Practical validation and profiling (Section V)

In this experiment we evaluated the practical feasibility of the proposed approach (i.e., the FRED framework).
Specifically, we showed that the framework can be implemented on a real-word platform (the Zynq-7010 System-on-Chip produced by Xilinx), on which hardware acceleration speed-up factors for a case-study application have been profiled and FPGA reconfiguration times have been measured.

Note: To replicate this experiment it necessary to dispose of the Zynq-7010 platform. In particular, the experiments have been performed on the Zybo board produced by Digilent.

Please follow THIS LINK to enter the page dedicated to such experiments.