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I'm a Ph.D. fellow at ReTiS Lab (Real-Time Systems Laboratory), Scuola Superiore Sant'Anna Pisa.

In 2014 I received my Bachelor's degree in Electronic Engineering and Computer Science from the University of Ferrara, Italy.

In Summer 2016 I partecipated as summer intern in the Fermilab Summer Intern programme.

In 2017 I received my Master's Degree, magna cum laude with honors, in Electronic Engineering and Telecommunications from the University of Ferrara, Italy.

During my education, I worked on solid state drives (SSD) analysis and simulations, Network on Chip (NoCs), AMBA AXI busses and resource management of heterogeneous resources.

My Ph.D. programme is mainly focused on enhancing the predictability of heterogenous systems, with a main focus on FPGA and FPGA SoCs.

Also, I'm working on hardware acceleration on FPGA SoC platforms for critical systems and exploring the neural network hardware acceleration on FPGA SoCs.

As a side project, I'm the current main developer and maintainer of the ReTiS Lab ARTe Arduino Real-Time extension


  • 10-July-2019: The paper "Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs" (Authors: Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo) has been accepted for pubblication at CASES 2019, within ESWEEK 2019 .


Francesco Restuccia,
Via G. Moruzzi 1, 56124 Pisa (PI), Italy
Scuola Superiore Sant'Anna (TeCiP Institute, ReTiS Laboratory)
francesco.restuccia (at) sssup (dot) it