I'm a Ph.D. fellow at ReTiS Lab (Real-Time Systems Laboratory), Scuola Superiore Sant'Anna Pisa.
In 2014 I received my Bachelor's degree in Electronic Engineering and Computer Science from the University of Ferrara, Italy.
In Summer 2016 I partecipated as summer intern in the Fermilab Summer Intern programme.
In 2017 I received my Master's Degree, magna cum laude with honors, in Electronic Engineering and Telecommunications from the University of Ferrara, Italy.
During my education, I worked on solid state drives (SSD) analysis and simulations, Network on Chip (NoCs), AMBA AXI busses and resource management of heterogeneous resources.
My Ph.D. programme is mainly focused on enhancing the predictability of heterogenous systems, with a main focus on FPGA and FPGA SoCs.
Also, I'm working on hardware acceleration on FPGA SoC platforms for critical systems and exploring the neural network hardware acceleration on FPGA SoCs.
As a side project, I'm the current main developer and maintainer of the ReTiS Lab ARTe Arduino Real-Time extension
From February 2020 to August 2020, I'm a Visting Ph.D. student at University of California, San Diego (UCSD), advised by Prof. Ryan Kastner.
- 26-March-2020: The paper "Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs" (Authors: Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo) has been accepted for pubblication at the 32th Euromicro Technical Committee on Real-Time Systems (ECRTS 2020) .
- 1-March-2020: The paper "Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC" (Authors: Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo) has been accepted for pubblication at the 28th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM 2020) .
- 11-February-2020: The paper "AXI HyperConnect: A Predictable, Hypervisor-level AXI Interconnect for Hardware Accelerators in FPGA SoC" (Authors: Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, and Giorgio Buttazzo) has been accepted for pubblication at the 57th Design Automation Conference (DAC 2020) .
Via G. Moruzzi 1, 56124 Pisa (PI), Italy
Scuola Superiore Sant'Anna (TeCiP Institute, ReTiS Laboratory)
francesco.restuccia (at) sssup (dot) it