I'm a PhD Fellow at Scuola Superiore Sant'Anna - Pisa (Italy).
In September 2013 I achieved the Bachelor's Degree in Computer Science Engineering at the University of Pisa with the score of 110/110.
In July 2016 I graduated cum laude in the Master of Science in Embedded Computing Systems, jointly offered by University of Pisa and Scuola Superiore Sant'Anna.
- 15-Nov-2018: The paper "Handling Transients of Dynamic Real-Time Workload Under EDF Scheduling" (Authors: Daniel Casini, Alessandro Biondi, and Giorgio Buttazzo) has been accepted for pubblication in IEEE Transactions on Computers.
- 39th IEEE Real-Time Systems Symposium, Nashville, Usa, December 11-14, 2018.
I authored two papers at the main conference:
Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo, "Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions".
Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo, "Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures".
- Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo, "Partitioned Fixed-Priority Scheduling of Parallel Tasks Without Preemptions".
- Secondary Reviewer for: RTAS 2017, EMSOFT 2018, RTSOPS 2018, RTSS 2018
- Member of the Technical Program Committee of: JRWRTC 2018
My research is focused on Real-Time Embedded Systems.
In particular I'm working on:
- Real-time operating systems
- Real-time schedulability analysis
- Synchronization protocols
- Component-based Software Design
- Predictability in AI-based Applications
Via G. Moruzzi 1, 56124 Pisa (PI), Italy
Scuola Superiore Sant'Anna (TeCiP Institute, ReTiS Laboratory)
Tel. +39 050 549 2043