Welcome! I'm a Post-Doc Researcher at Scuola Superiore Sant'Anna - Pisa (Italy). In July 2020 I received (with honors) the PhD in Emerging Digital Technologies (curriculum Embedded Systems) at Scuola Superiore Sant'Anna, where I worked at the ReTiS Lab under the supervision of Prof. Giorgio Buttazzo and Prof. Alessandro Biondi. In 2019 I visited the Max Planck Institute for Software Systems - Kaiserslautern (Germany), where I worked with Björn Brandenburg. In July 2016 I graduated cum laude in the Master of Science in Embedded Computing Systems, jointly offered by University of Pisa and Scuola Superiore Sant'Anna. In September 2013 I achieved the Bachelor's Degree in Computer Science Engineering at the University of Pisa with the score of 110/110.

News

• 09-Oct-2020: I will serve in the TPC of ISORC 2021.
• 02-Jul-2020: I received the PhD degree in Emerging Digital Technologies, curriculum Embedded Systems, with honors.
• 27-Mar-2020: The paper "Demystifying the Real-Time Linux Scheduling Latency" (Authors: Daniel Bristot de Oliveira, Daniel Casini, Rômulo Silva de Oliveira, and Tommaso Cucinotta) has been accepted for publication in ECRTS 2020 .
• 25-Mar-2020: The paper "Timing Isolation and Improved Scheduling of Deep Neural Networks for Real-Time Systems" (Authors: Daniel Casini, Alessandro Biondi, and Giorgio Buttazzo) has been accepted for publication in Software: Practice and Experience.
• 11-Feb-2020: The paper "Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks" (Authors: Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale, and Giorgio Buttazzo) has been accepted for publication in DAC 2020.
• 29-Jan-2020: The paper "A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling" (Authors: Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo) has been accepted for publication in RTAS 2020.

Upcoming or recent events

• 57th ACM/ESDA/IEEE Design Automation Conference (DAC 2020), San Francisco, CA, USA , July 19-23, 2020. I authored one paper at the main conference:
  1. Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale, and Giorgio Buttazzo, "Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks".
     
• 32th Euromicro Conference on Real-Time Systems (ECRTS 2020), Modena, Italy, July 7-10, 2020. I authored one paper at the main conference:
  1. Daniel Bristot de Oliveira, Daniel Casini, Rômulo Silva de Oliveira, and Tommaso Cucinotta, "Demystifying the Real-Time Linux Scheduling Latency".
     
  
  I will serve in the Artifact Evaluation Committee.
• 14th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2020), in conjunction with RTNS 2020, , Paris, France, June 9, 2020. I will serve in the Workshop Committee.

Service

• Member of the Technical Program Committee of:
  • Conferences: ISORC 2021, ISORC 2020
  • Workshops:JRWRTC 2020, RTAS 2020 (Brief Presentations), RTAS 2019 (Brief Presentations), JRWRTC 2018
  • Artifact Evaluations: ECRTS 2020, ECRTS 2019, RTAS 2019
• Reviewer for international journals: Springer Real-Time Systems Journal, ACM Transactions on Embedded Computing Systems (TECS), IEEE Transaction on Emerging Topics in Computing, Journal of Systems and Software, Journal of Systems Architecture, IEEE Embedded Systems Letters
• Secondary Reviewer for international conferences: RTSS 2020, EMSOFT 2020, RTCSA 2020, DAC 2020, RTAS 2020, RTSS 2019, EMSOFT 2019, ECRTS 2019, DAC 2019, Eurosys 2019, RTAS 2019, RTSS 2018, RTSOPS 2018, EMSOFT 2018, RTAS 2017
• Secondary Reviewer for international journals: IEEE Transactions on Parallel and Distributed Systems, SN Computer Science, SN Applied Science

Research Interests

My research is focused on Real-Time Embedded Systems.
In particular I'm working on:

• Real-time operating systems
• Real-time schedulability analysis
• Synchronization protocols
• Component-based Software Design
• Predictability in AI-based Applications

Contacts

Daniel Casini,
Via G. Moruzzi 1, 56124 Pisa (PI), Italy
Scuola Superiore Sant'Anna (TeCiP Institute, ReTiS Laboratory)
Tel. +39 050 88 2078
daniel.casini@sssup.it