Welcome! I'm a PhD Fellow at Scuola Superiore Sant'Anna - Pisa (Italy). In September 2013 I achieved the Bachelor's Degree in Computer Science Engineering at the University of Pisa with the score of 110/110. In July 2016 I graduated cum laude in the Master of Science in Embedded Computing Systems, jointly offered by University of Pisa and Scuola Superiore Sant'Anna. In October 2016 I joined the ReTiS Lab, working under the supervision of Prof. Giorgio Buttazzo and Prof. Alessandro Biondi. In 2019 I visited the Max Planck Institute for Software Systems - Kaiserslautern (Germany), where I worked with Björn Brandenburg.

News

• 11-Feb-2020: The paper "Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks" (Authors: Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale, and Giorgio Buttazzo,) has been accepted for publication in DAC 2020.
• 29-Jan-2020: The paper "A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling" (Authors: Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo) has been accepted for publication in RTAS 2020.
• 31-Oct-2019: The paper "A Safe, Secure, and Predictable Software Architecture for Deep Learning in Safety-Critical Systems" (Authors: Alessandro Biondi, Federico Nesti, Giorgiomaria Cicero, Daniel Casini, and Giorgio Buttazzo) has been accepted for publication in IEEE Embedded Systems Letters.

Upcoming or recent events

• 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020) , Sydney, Australia, April 21-24, 2020. I authored one paper at the main conference:
  1. Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, and Giorgio Buttazzo, "A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling".
     
• 31th Euromicro Conference on Real-Time Systems (ECRTS 2019), Stuttgart, Germany, July 9-12, 2019. I authored three contributions:
  1. Main Conference: Daniel Casini, Tobias Blaß, Ingo Lütkebohle, and Björn B. Brandenburg, "Response-Time Analysis of ROS 2 Processing Chains under Reservation-Based Scheduling".
     
  2. WATERS 2019: Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Giorgio Buttazzo and Marco Di Natale, "Addressing Analysis and Partitioning issues for the WATERS 2019 Challenge".
     
  3. Journal to Conference Presentation: Daniel Casini, Alessandro Biondi, and Giorgio Buttazzo, "Handling Transients of Dynamic Real-Time Workload Under EDF Scheduling".
     
• 56th ACM/ESDA/IEEE Design Automation Conference (DAC 2019), Las Vegas, NV, USA , June 2-6, 2019. I authored one paper at the main conference:
  1. Daniel Casini, Alessandro Biondi, and Giorgio Buttazzo, "Analyzing Parallel Real-Time Tasks Implemented with Thread Pools".
     

Service

• Member of the Technical Program Committee of: ISORC 2020, RTAS 2020 (Brief Presentations), ECRTS 2019 (Artifact Evaluation), RTAS 2019 (Brief Presentations), RTAS 2019 (Artifact Evaluation), JRWRTC 2018
• Reviewer for international journals: Springer Real-Time Systems Journal, ACM Transactions on Embedded Computing Systems (TECS), IEEE Transaction on Emerging Topics in Computing, Journal of Systems and Software
• Secondary Reviewer for international conferences: RTAS 2020, RTSS 2019, EMSOFT 2019, ECRTS 2019, DAC 2019, Eurosys 2019, RTAS 2019, RTSS 2018, RTSOPS 2018, EMSOFT 2018, RTAS 2017
• Secondary Reviewer for international journals: IEEE Transactions on Parallel and Distributed Systems, SN Computer Science

Research Interests

My research is focused on Real-Time Embedded Systems.
In particular I'm working on:

• Real-time operating systems
• Real-time schedulability analysis
• Synchronization protocols
• Component-based Software Design
• Predictability in AI-based Applications

Contacts

Daniel Casini,
Via G. Moruzzi 1, 56124 Pisa (PI), Italy
Scuola Superiore Sant'Anna (TeCiP Institute, ReTiS Laboratory)
Tel. +39 050 549 2043
daniel.casini@sssup.it